A network processor generally controls the flow of data between a physical transmission medium, such as a physical layer portion of a network, and a switch fabric in a router or other type of switch.
It is often advantageous to configure a network processor to include one or more Ethernet MACs. For example, such MACs can be used to accommodate applications in which an asynchronous transfer mode (ATM) or Internet protocol (IP) network connection needs to be terminated to an Ethernet link.
An Ethernet MAC suitable for supporting Gigabit Ethernet or Fast Ethernet data traffic has two primary functional units, namely, a transmit unit and a receive unit. A typical conventional MAC implementation generally provides a close physical coupling between the two units. More specifically, the two units are usually not physically separated from one another, but are instead located in the same region of a given integrated circuit, also referred to herein as a chip.
The MAC transmit and receive units must interface to application logic that may be located in other regions of the chip. In a given implementation, the MAC application logic interface for Gigabit Ethernet or Fast Ethernet may be, for example, on the order of about 70 bits wide, per transmit and receive side. Because the conventional MAC typically resides in a single location, the entire application logic interface has to be routed from the part of the chip where the MAC is located to the part of the chip where the application logic that connects to the MAC transmit and receive units is located. As the size of the chip increases, this creates a significant problem due to the large number of routes that have to traverse long distances. The problem becomes even worse when there are multiple MACs on a single integrated circuit.
One may attempt to overcome the above-described application logic interface problem by physically separating the MAC transmit and receive units, so that each may be located in proximity to its associated application logic. For example, the transmit and receive units may be placed in opposite corners of the chip. An arrangement of this type is generally referred to as a “split” transmit and receive MAC. Unfortunately, a similar routing problem arises when interfacing the physically-separated transmit and receive units. There are a significant number of signals required in the interface between the transmit and receive units for each Gigabit Ethernet or Fast Ethernet MAC. This interface requirement also makes it impractical to locate MAC transmit and receive units on different chips, since the interface between the units will require an excessive number of input-output circuits. Again, the severity of the problem increases dramatically with the number of MACs that are required in the design.
It is therefore apparent that a need exists for improved techniques for implementing Ethernet MACs in network processor integrated circuits and other applications, so as to reduce the amount of chip resources that are consumed by the MAC interfaces.